Scientific Context
Direct-to-Satellite Internet of Things (DtS-IoT) technologies enable low-cost, battery-powered, low-power devices to communicate directly with a satellite in low Earth orbit at approximately 500 km altitude. This enables the transmission of low-data-rate information from remote geographic areas where no terrestrial infrastructure, such as a base station, is available [UMA23]. Examples of applications for these technologies include tracking containers during maritime transport and precision agriculture.
DtS-IoT communications present several challenges for the uplink, meaning communication from the connected device to the satellite. First, the speed of orbiting satellites, approximately 8 km/s, produces a significant Doppler shift that alters the carrier frequency of the received signals, creating a frequency synchronization issue. In addition, interference exists between signals originating from different transmitters. Finally, communication with low-cost transmitters over several hundred kilometers results in a very low signal-to-noise ratio, or SNR.
Among existing DtS-IoT technologies, LR-FHSS, or Long-Range Frequency-Hopping Spread Spectrum [BTA+21], stands out for its ability to serve a large number of connected devices in parallel, as well as for its robustness against interference and the Doppler effect. Many research works propose LR-FHSS receivers or receiver blocks, along with various improvements to this technology at the medium access control layer. However, few works have been reported on hardware implementation.
Objective
The purpose of this internship is to study the performance of an LR-FHSS receiver chain using the following metrics: execution speed, memory footprint, telecommunication performance (packet error rate), and energy consumption. An LR-FHSS receiver chain and simulated received signals will be provided to the intern. The intern’s objective will be to optimize the receiver-chain algorithm to examine the trade-offs among the four metrics listed above.
Internship Organization
The internship is expected to proceed as follows:
- The intern will first study the provided receiver chain.
- The intern will then propose various modifications to the receiver chain, based on their understanding of it, while exploring the possible trade-offs between the four metrics mentioned above. This could include for example:
- studying various levels of quantization precision for the variables used;
- studying different schemes for distributing computations between FPGA and CPU on a heterogeneous architecture;
- Comparing the performance of different hardware architectures.
Profile
We are looking for a Master’s student (M2 level) or equivalent, specializing in electronics or embedded systems. The candidate should have solid knowledge of hardware architecture and parallel programming, as well as proficiency in C programming. Familiarity with basic aspects of signal processing, particularly the discrete Fourier transform (DFT/FFT) and digital filtering, would be appreciated.
Internship Conditions
- Duration: 5 to 6 months, starting in September 2026.
- Compensation: In accordance with legal internship regulations (€4.50 net/hour, approximately €630/month for 35 hours/week)
- Location: Laboratoire des Signaux et Systèmes – UMR 8506.
Application
Please send your detailed CV and a cover letter to:
- Marwane Rezzouki: marwane.rezzouki@centralesupelec.fr
References
[UMA23] Muhammad Asad Ullah, Konstantin Mikhaylov, and Hirley Alves. An overview of direct-to-satellite IoT: Opportunities and open challenges. In 2023 IEEE 9th World Forum on Internet of Things (WF-IoT), pages 1–8. IEEE, 2023.
[BTA+21] Boquet, G., Tuset-Peiró, P., Adelantado, F., Watteyne, T., & Vilajosana, X. (2021). LR-FHSS: Overview and performance analysis. IEEE Communications Magazine, 59(3), 30–36.
