Réunion

Dominique GINHAC - LE2I (Dijon)

Architectures embarquées pour l'imagerie HDR en temps réel

Les caméras standard sont incapables de capturer la dynamique d'une scène naturelle. Malgré des performances sans cesse croissantes, les caméras standards ont des difficultés à capturer la dynamique d'une scène naturelle, entrainant inévitablement des zones saturées. L'imagerie à grande dynamique propose donc différentes techniques permettant de capturer une plus grande dynamique et ainsi obtenir de l?information pertinente dans les zones très sombres ou fortement éclairées de la scène. Pour obtenir la plus grande gamme dynamique de la scène, la technique classiquement utilisé est l'acquisition successive de plusieurs images de la scène en faisant varier l'exposition. Cet ensemble d'images est ensuite combiné afin de produire l'image finale à grande dynamique. Si de nombreuses solutions algorithmiques ont été développées en particulier dans le cadre d'applications grand public de photo numérique, il existe peu de travaux à l'heure actuelle sur la conception matérielle de systèmes de vision dédiés capables de produire en temps réel du contenu à grande dynamique. Cette présentation aura pour objectif de présenter les travaux effectués par notre équipe sur le développement et la mise au point de plusieurs caméras intelligentes capables de capturer des vidéos grande dynamique. La mise au point de ces systèmes matériels et logiciels implique donc de mettre en place une démarche d'Adéquation Algorithme Architecture permettant d'adapter à la fois la chaîne de traitement d'images et le système matériel d'acquisition et de traitement permettant ainsi de tirer parti des possibilités d'acquisition de contenu à grande dynamique.

Wissam Benjilali, William Guicquero, Gilles Sicard (CEA leti), Laurent Jacques (UCL) -CEA LETI

On compressive sampling strategies for near image sensor decision making

We present some scenarios to address near sensor decision making based on Dimensionality Reduction (DR) techniques of high dimensional signals in the context of highly constrained hardware (eg., low power vision systems). The studied DR techniques are learned according to two alternative strategies: one whose parameters are learned in a compressed signal representation, as being achieved by random projections in a compressive sensing device, the other being performed in the original uncompressed signal domain. For both strategies, the inference is yet indifferently performed in the compressed domain with dedicated algorithm depending on the selected learning technique.

Jonathan Bonnard, Francois Berry, Kamel Abdelouahab, Maxime Pelcat (DREAM Institut Pascal, Université Clermont Auvergne)

A novel multi view smart camera framework based on FPGA for deep learning

In this work, we propose a multiple view smart camera. This device is made by several image sensors connected to a common FPGA-based processing unit. Obviously, these sensors can be synchronized (or not) and provided a non-conventional sequences of images. Moreover, a pre- processing is performed within each image sensors and all processed flows are merged on a larger processing unit. From this new device, we propose to split and reduce the conventional CNN. Indeed, we postulate that a multiple view of an object (or a scene) is a richer input for classification process. In this way, it could be feasible to reduce the deep learning network while keeping a good classification ratio.

Stéphane Chevobbe (CEA LIST - Saclay)

Demonstration of a 3D stacked BSI vision chip

We present a demonstration of a 3D stacked vision chip featuring in-focal-plane readout tightly coupled with flexible computing architecture for configurable high speed image analysis.

By using 3D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and processing elements for low latency performances, while leaving enough room in the bottom tier to embed advanced computing features.

We demonstrate the main characteristics of this chip :

- Low latency processing

- High flexibility processing

- Complex processing

by the execution of several complex functions like multi-instruction flow, edge detection and fast event detection.

Jean Philippe DIGUET - Lab-STICC Lorient

Systèmes embarqués autonomes pour véhicules autonomes

Résumé à venir

Yang NI - New Imaging Technologies ?

Multi-mode Logarithmic Sensor for Smart Vision Systems

Logarithmic response permits to index the image signal directly to the scene contrast. This property gives stable scene representation, even under difficult illumination conditions. We have developed a logarithmic pixel design by using photodiode in solar-cell mode. This pixel design eliminates the strong Fixed Pattern Noise and image lag problems and gives image signal which can be directly used by image processing unit. This paper presents a 640x480-pixel multi-mode logarithmic sensor realized in 0.18um CMOS technology. The global architecture is composed of a 648x488-pixel array, a programmable timing generator and a 12-bit fast column ADC. The digital data are output in low voltage single end format.

The pixel includes a solar-cell mode photodiode, a reset transistor, a buffer amplifier and also an analogue memory connected to a selectable bus driving buffer. The selected pixel line is fed to a 12-bit SAR column ADC. The converted digital data is stored in a RAM and scanned out by a horizontal shift register. The user programmable timing generator generates all the control signals to operate the pixel array in 3 different modes: 1) progressive readout mode (equivalent to rolling shutter mode); 2) global shutter mode; 3) frame to frame differential mode and 4) background suppression mode.

In progressive readout mode, the in-pixel memory is connected constantly to photodiode buffer amplifier. For each selected line, double readouts with reset transistor off and on remove the fixed pattern noise induced by the readout chain. A continuous video is provided. In global shutter mode, the image signal from solar-cell mode photodiode is sampled to the in-pixel memory before the frame readout. So the motion distortion is eliminated in this mode. These two modes are very similar to classic CMOS image sensors largely used in machine vision.

The differential mode and the background suppression modes are unique in this sensor. When the sensor is configured in differential mode, each selected pixel line will be operated as following: the analogue memory is read at first, then the photodiode buffer amplifier?s output is sampled to the analogue memory which is read again. The column ADC will convert the difference between these read results into digital data which represents the frame to frame change. A non-zero value will be generated when there is a change in the scene. The background suppression mode works in the following way: all the photodiodes are reset and then exposed to the scene. At the end of the exposure, photodiode outputs are sampled into the in-pixel memories. The image readout will be line by line based. When a line is selected, the analogue memory is read out at first and then the photodiode will be reset and exposed to the scene with a same duration as the initial global exposure. The photodiode signal is sampled to the analogue memory and read again.

All these modes can be configured in a frame-to-frame base. The progressive and global shutter modes can be used to capture the image of scene. The differential mode generates an image which highlights the changes in a scene. This differential image can be used in various applications such surveillance, stereo vision, object counting, etc. Since it?s realized inside the pixel, so neither extra computation power nor memory is needed. The background suppression mode can be used with a pulsed illumination to remove the static background. It can be used for remove the influence of ambient light in machine vision applications.

A demo camera will be exposed during the forum in order to trigger fruitful discussion for smart vision systems and applications.

Juliette LEHIR - GeePs - Laboratoire de Génie électrique et électronique de Paris

Conception mixte d?un imageur intelligent intégré à traitements locaux massivement parallèles

Transmettre de l?information pertinente en sortie de capteur tout en assurant une versatilité et une qualité d?image suffisantes ? C?est la problématique à laquelle ces travaux tentent d?apporter quelques réponses. L?imageur intelligent présenté ici intègre des prétraitements réalisés dès la matrice de pixels. Les calculs de type convolution spatiale ou détection de mouvement, sont distribués au niveau macropixel (groupe de pixels) et ont été adaptés à cette architecture (principe d?AAA). L?implémentation proposée de l?élément de calcul est en circuit à capacités commutées : analogique pour limiter la consommation en énergie et la surface occupée entre les pixels, mais programmable grâce à un circuit numérique extérieur à la matrice pour garantir la versatilité du circuit. Une approche algorithmique par calcul approximé, validée en amont, a permis un dimensionnement minimisant sa surface. La matrice dessinée présente un facteur de remplissage de 28% et des simulations en vue extraite permettent d?atteindre de bons résultats de détection de contours ou de mouvement.

Satyajit Das - Lab-STICC Lorient

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

Due to increasing demand of low power computing, and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy-efficient programmable accelerators. This paper proposes an Integrated Programmable-Array accelerator (IPA) architecture based on an innovative execution model, targeted to accelerate both data and control-flow parts of deeply embedded vision applications typical of edge-nodes of the Internet of Things (IoT). In this paper we demonstrate the performance and energy efficiency of IPA implementing a smart visual trigger application. Experimental results show that the proposed accelerator delivers 507 MOPS and 142 MOPS/mW on the target application, surpassing a low-power processor optimized for DSP applications by 6x in performance and by 10x in energy efficiency. Moreover, it surpasses performance of state of the art CGRAs only capable of implementing data-flow portion of applications by 1.6x, demonstrating the effectiveness of the proposed architecture and computational model.

Mathieu THEVENIN - Université Paris-Saclay, CEA IRAMIS SPEC

eISP, a fully programmable architecture for image and signal processing

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities - several dozens of GOPs for real-time HD
1080p video streams. Today's embedded designs constraints impose limitations both in terms of silicon budget and power consumption - usually 2 mm2 for half a Watt. The eISP architecture presented in this work is able to reach
188 MOPs/mW with 94 GOPs/mm2 and 378 GOPs/mW using TSMC 65 nm integration technology. This fully programmable and modular architecture, has been built on an analysis of video processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplifies the architecture sizing and characterization. The results obtained in this work are compared to the state-of-the art architecture and evolution toward different forms of signal processing are drawn at the end of the presentation.