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[DASIP 2026] Call for Papers — deadline 17 November 2025

03 Octobre 2025


Catégorie : Conférence internationale ;

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Call for Paper

The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud
computing architectures and systems.

The workshop program will include keynote speeches and contributed paper sessions. The 19th edition will be held in conjunction with the 21st HiPEAC Conference in Kraków, Poland, January 26-28, 2026.

Important dates (all 23:59 A.O.E)

Main cycle

  • Abstract submission deadline : 10 November 2025
  • Paper submission deadline : 17 November 2025
  • Notification of acceptance : 19 December 2025
  • Camera-ready papers : 17 January 2026
  • Workshop : 27 to 28 January 2026

Venue

The Workshop on Design and Architectures for Signal and Image Processing will be held in conjunction with the 21st HiPEAC Conference in Kraków, Poland, 26 to 28 January 2026. The workshop itself will be held 27 and 28 January 2026.

Registration

DASIP 2026 is a HiPEAC-based workshop. Hence, a registration at HiPEAC is required. Please be aware that for each accepted paper, at least, one of the authors must pay the full registration fee in order for the paper to be included in the workshop proceedings and scheduled in the program.

Submission guidelines

Authors should submit their full papers (up to 12 pages) in the single-column Springer LNCS format in PDF through the DASIP HotCRP system.
Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work. Instead, they need to make self-references in the third person. More
details on submission requirements, templates, and submission instructions are provided on the DASIP website.

The submission process is in two cycles: the now-closed preliminary one, and the main one. Having submitted to the preliminary cycle is not mandatory. Only the main cycle is definitive. Authors who have received an early acceptance notice from the preliminary cycle do not need to submit their paper to
the main cycle. A rejected preliminary-cycle paper can be resubmitted after correction. Besides, new submissions can be done without consideration for the preliminary cycle.

Each submission will receive at least three independent double-blind reviews from the members of our scientific committee. Authors are encouraged to take the reviewers’ comments into account when they
prepare the final versions of their papers and present the research during the workshop before its publication. The conference proceedings will be published in the Springer LNCS Series, on the Springer Link website. Paper and keynote presentation slides and tutorial documents will be made available to workshop attendees after the workshop (subject to confidentiality issues).

Contact

All questions about the workshop and submissions should be emailed to Marcin KOWALCZYK <kowalczyk@agh.edu.pl> or Camille MONIÈRE <camille.moniere@univ-ubs.fr>.

List of topics

Prospective authors are invited to submit manuscripts on topics including, but not limited to:

  • Custom embedded, edge and cloud architectures and systems:
    • Machine learning and deep learning architectures for inference and training
    • Systems for autonomous vehicles : cars, drones, ships and space applications
    • Image processing and compression architectures
    • Smart cameras, security systems, behaviour recognition
    • Edge and cloud processing: special routing, configurable co-processors, and low energy considerations
    • Real-time cryptography, secure computing, financial and personal data processing
    • Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
    • Biological data collection and analysis, bioinformatics
    • Personal digital assistants, natural language processing, wearable computing and implantable devices
    • Global navigation satellite and inertial navigation systems
  • Design Methods and Tools:
    • Design verification and fault tolerance
    • Embedded system security and security validation
    • System-level design and hardware/software co-design
    • High-level synthesis, logic synthesis, communication synthesis
    • Embedded real-time systems and real-time operating systems
    • Rapid system prototyping, performance analysis and estimation
    • Formal models, transformations, algorithm transformations and metrics
  • Development Platforms, Architectures and Technologies:
    • Embedded platforms for multimedia and telecommunication
    • Many-core and multi-processor systems, SoCs, and NoCs
    • Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
    • Memory system and cache management
    • Asynchronous (self-timed) circuits and analog and mixed-signal circuits

Organization

Chairs

  • Marcin KOWALCZYK, AGH University of Kraków, Kraków, Poland
  • Camille MONIÈRE, Université Bretagne Sud / Lab-STICC UMR 6285, Lorient, France

Steering committee

  • Alfonso RODRÍGUEZ, Universidad Politécnica de Madrid, Madrid, Spain
  • Andrea PINNA, Sorbonne University, Paris, France
  • Diana GOEHRINGER, TU Dresden, Dresden, Germany
  • Jean-Pierre DAVID, École Polytechnique de Montreal, Montreal, Canada
  • Joao M. P. CARDOSO, University of Porto, Porto, Portugal
  • Karol DESNOS, INSA Rennes – IETR laboratory, Rennes, France
  • Marek GORGON, AGH University of Science and Technology, Kraków, Poland
  • Miguel CHAVARRÍAS, Universidad Politécnica de Madrid, Madrid, Spain
  • Michael HUEBNER, Brandenburg University of Technology, Cottbus-Senftenberg, Germany
  • Tomasz KRYJAK, AGH University of Science and Technology, Kraków, Poland
  • Paolo MELONI, University of Cagliari, Cagliari, Italy
  • Sergio PERTUZ, TU Dresden, Dresden, Germany
  • Sebastien PILLEMENT, University of Nantes – IETR, Nantes France

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